About
Professional SummaryDr. Sivanantham Sathasivam is currently working as Associate Professor at VIT University, India. He received his Ph.D. in Microelectronics from same University. His main area of interest related to Physical Science Engineering, and Computer Sciences. His area of expertise includes Computer Architecture, Asic Design, Low Power Vlsi Design, Vlsi Testing, Vlsi Design, DSP Architectures, Fault Tolerant Systems, Test Data Compression, Fgpa, High Speed Design, Microelectronics, Partial Reconfiguration, Reconfigurable Architectures, Design For Testability, Computer Arithmetic, and Digital System Design. He is author and co-author of 35 journals papers.
Education
Academic Background-
Ph.D. Vellore Institute of Technology University, India VLSI Design and Testing | Completed: 2014
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Ph.D. VIT University, India VLSI Design | Completed: 2006
Publications (24)
Selected Scholarly Contributions
Compact pattern set generation for accelerated small delay defect testing
2024
Optimal Test Clock Frequency Based Test Option Generation for Small Delay Defects
2023
2023
Advanced TSV-BIST Repair Technique to Target the Yield and Test Challenges in 3-D Stacked IC’S
2022
2022
Quality Assessment of Dual-Parallel Edge Deblocking Filter Architecture for HEVC/H.265
2022
2022
Efficient half-precision floating point multiplier targeting color space conversion
2020
Low-Error Reconfigurable Fixed-Width Multiplier for Image Processing Applications
2020
High-Throughput Deblocking Filter Architecture Using Quad Parallel Edge Filter for H.264 Video Coding Systems
2019
Two-stage low power test data compression for digital VLSI circuits
2018
2017
2015
Partial reconfigurable implementation of IEEE802.11g OFDM.
Sivanantham Sathasivam
2014
ASIC implementation of two stage pipelined multiplier.
Sivanantham Sathasivam
2014
ASIC implementation of low power universal asynchronous receiver transmitter.
Sivanantham Sathasivam
2014
Efficient floating point multiplier implementation via carry save multiplier.
Sivanantham Sathasivam
2014
Low-power selective pattern compression for scan-based test applications.
Sivanantham Sathasivam
2014
Enhancement of test data compression with multistage encoding.
Sivanantham Sathasivam
2014
Design of low power floating-point multiplier with reduced switching activity in deep submicron technology.
Sivanantham Sathasivam
2013
Design of floating point multiplier for signal processing applications.
Sivanantham Sathasivam
2013
System-on-a-chip test data compression and decompression with reconfigurable serial multiplier.
Sivanantham Sathasivam
2013
Low power floating point computation sharing multiplier for signal processing applications.
Sivanantham Sathasivam
2013
A survey on single and double edge-triggered flip-flops to design scan flip-flop cell.
Sivanantham Sathasivam
2010