Dr. S.  Sivanantham
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Dr. S. Sivanantham

Associate Professor and Assistant Director
VIT University, India


Highest Degree
Ph.D. in VLSI Design from VIT University, India

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Biography

Dr. S. Sivanantham is currently working as Associate Professor at VIT University, India. He received his Ph.D. in Microelectronics from same University. His main area of interest related to Physical Science Engineering, and Computer Sciences. His area of expertise includes Computer Architecture, Asic Design, Low Power Vlsi Design, Vlsi Testing, Vlsi Design, DSP Architectures, Fault Tolerant Systems, Test Data Compression, Fgpa, High Speed Design, Microelectronics, Partial Reconfiguration, Reconfigurable Architectures, Design For Testability, Computer Arithmetic, and Digital System Design. He is author and co-author of 35 journals papers.

Area of Interest:

Computer Sciences
100%
Computer Architecture
62%
VLSI Design
90%
Fault-Tolerant Systems
75%
Digital Systems
55%

Research Publications in Numbers

Books
0
Chapters
0
Articles
0
Abstracts
0

Selected Publications

  1. Kansagara, K., K.V. Shravya and S. Sivanantham, 2015. Dynalic Reconfigurable Architectures: A Boon for Desires of Real Time Systems. In: Information Systems Design and Intelligent Applications, Mandal, J.K., S.C. Satapathy, M.K. Sanyal, P.P. Sarkar and A. Mukhopadhyay (Eds.). Springer, India, ISBN: 978-81-322-2246-0, pp: 235-244.
  2. Abhinav, B.S., M.J. Reddy, Y.S. Kumar and S. Sivanantham, 2015. ASIC design of reversible adder and multiplier. Int. J. Comput. Applic., 109: 6-10.
    CrossRef  |  Direct Link  |  
  3. Suresh, B., P.T. Reddy, V.S.V. Srihari and S. Sivanantham, 2014. ASIC implementation of low power universal asynchronous receiver transmitter. World Applied Sci. J., 32: 472-477.
  4. Sivanantham, S., R. Adarsh, S. Bhargav and K.J. Naidu, 2014. Partial reconfigurable implementation of IEEE802.11g OFDM. Indian J. Sci. Technol., 7: 63-70.
    Direct Link  |  
  5. Sivanantham, S., P.S. Mallick and J.R.P. Perinbam, 2014. Low-power selective pattern compression for scan-based test applications. Comput. Electr. Eng., 40: 1053-1063.
    CrossRef  |  Direct Link  |  
  6. Sivanantham, S., M. Padmavathy, G. Gopakumar, P.S. Mallick and J.R.P. Perinbam, 2014. Enhancement of test data compression with multistage encoding. Integration VLSI J., 47: 499-509.
    CrossRef  |  Direct Link  |  
  7. Singh, H., R. Heena and S. Sivanantham, 2014. ASIC implementation of two stage pipelined multiplier. Int. J. Eng. Res. Technol., 3: 1464-1466.
  8. Kumar, P.S., A. Verma, C. Patel and S. Sivanantham, 2014. Efficient floating point multiplier implementation via carry save multiplier. Middle-East J. Scient. Res., 22: 1652-1657.
    Direct Link  |  
  9. Agarwal, A., P. Harsha, S. Vasishta and S. Sivanantham, 2014. Implementation of special function unit for vertex shader processor using hybrid number system. J. Comput. Networks Commun., Vol. 2014. 10.1155/2014/890354.
    CrossRef  |  Direct Link  |  
  10. Sivanantham, S., M. Padmavathy, S. Divyanga and P.V.A. Lincy, 2013. System-on-a-chip test data compression and decompression with reconfigurable serial multiplier. Int. J. Eng. Technol., 5: 973-978.
  11. Sivanantham, S., K.J. Naidu, S. Balamurugan and D.B. Phaneendra, 2013. Low power floating point computation sharing multiplier for signal processing applications. Int. J. Eng. Technol., 5: 979-985.
    Direct Link  |  
  12. Sivanantham, S., 2013. Design of low power floating-point multiplier with reduced switching activity in deep submicron technology. Int. J. Applied Eng. Res., 8: 715-722.
  13. Babu, A.R., R. Saikiran and S. Sivanantham, 2013. Design of floating point multiplier for signal processing applications. Int. J. Applied Eng. Res., 8: 715-722.
  14. Valibaba, D.S. and S. Sivanantham, 2010. A survey on single and double edge-triggered flip-flops to design scan flip-flop cell. Programmable Device Circuits Syst., 2: 163-170.
    Direct Link  |