Dr. Rishu  Chaujar
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Dr. Rishu Chaujar

Assistant Professor
Delhi Technological University, India


Highest Degree
Ph.D. in Electronics from University of Delhi, Delhi, India

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Biography

Dr. Rishu Chaujar is currently working as Assistant Professor at Delhi Technological University, India. She has completed her Ph.D. in Electronics from University of Delhi, Delhi, India. Previously she was appointed as Design Engineer in Saora Informatics India Pvt Ltd., Nehru Place, and Lecturer at University of Delhi. Dr. Rishu received honors includes Young Scientist Award for contribution in the field of Microelectronics, 2nd Academic Brilliance Award, Pearson Teaching Award, DST Fast Track Young Scientist Award, and many others. She is also serving as reviewer for Microsystem Technologies Journal, Elsevier, Progress in Electromagnetic Research Journal, USA, Oxford University Press for Few chapters of book on Engineering Physics, Microelectronics Journal, Journal of Electronics and Electrical Engineering Research, International Journal of Physical Sciences, and International Journal of Numerical Modeling. She is editor for Journal of Embedded Systems, Science and Education Publishing, USA and member of advisory board in Journal of Electronic and Electrical Engineering. She is life member of Indian Society for Technical Education, Institution of Electronics & Telecommunication Engineers (IETE), India, Indian Women Scientists’ Association, India, Indian Science Congress Association, India, Semiconductor Society of India, India, Materials Research Society of India and member of IEEE Communication Society, USA, International Association of Engineers, Hong Kong, IEEE Professional Organization, USA, American Nano Society, USA, Green ICT Community, IEEE, IEEE Council on RFID, executive member of IEEE Electron Devices Society. She has supervised 10 M.Tech students and 5 PhD currently in her supervision. She has published 154 research articles in journals and conference contributed as author/co-author.

Area of Interest:

Physical Science Engineering
100%
Microstructure
62%
Applied Physics
90%
Electrical Engineering
75%
Microwave Engineering
55%

Research Publications in Numbers

Books
0
Chapters
0
Articles
0
Abstracts
0

Selected Publications

  1. Kumar, A., N. Gupta and R. Chaujar, 2016. TCAD RF performance investigation of transparent gate recessed channel Mosfet. Microelectron. J., 49: 36-42.
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  2. Kumar, A., N. Gupta and R. Chaujar, 2016. Power gain assessment of ITO based transparent gate recessed channel (TGRC) Mosfet for RF/wireless applications. Superlattices Microstruct., 10.1016/j.spmi.2016.01.027.
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  3. Ahmad, S., J. Shah, A.K. Katiyar, R. Chaujar, N.K. Puri, P.S. Negi and R.K. Kotnala, 2016. Microwave device jig characterization for ferromagnetic resonance induced spin hall effect measurement in bilayer thin films. Indian J. Pure Appl. Phys., 54: 60-65.
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  4. Pandey, R. and R. Chaujar, 2015. Novel back-contact back-junction SiGe (BC-BJ SiGe) solar cell for improved power conversion efficiency. Microsyst. Technol., 10.1007/s00542-015-2552-1.
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  5. Madan, J., R.S. Gupta and R. Chaujar, 2015. Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor. Jpn. J. Appl. Phys., Vol. 54. 10.7567/JJAP.54.094202.
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  6. Kumar, A., N. Gupta and R. Chaujar, 2015. Analysis of novel transparent gate recessed channel (TGRC) Mosfet for improved analog behaviour. Microsyst. Technol., 10.1007/s00542-015-2554-z.
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  7. Gupta, N., A. Kumar and R. Chaujar, 2015. Oxide bound impact on hot-carrier degradation for gate electrode workfunction engineered (GEWE) silicon nanowire Mosfet. Microsyst. Technol., 10.1007/s00542-015-2557-9.
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  8. Gupta, N., A. Kumar and R. Chaujar, 2015. Impact of device parameter variation on RF performance of gate electrode workfunction engineered (GEWE)-silicon nanowire (SiNW) Mosfet. J. Comput. Electron., 14: 798-810.
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  9. Sinha, A.K. and R. Chaujar, 2014. Luminous TCAD analysis of transparent ITO gate recessed channel Mosfet using elliptical lenslet. Int. J. Comput. Applic. Eng. Sci., 4: 17-25.
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  10. Pandey, R. and R. Chaujar, 2014. Enhanced back-contact back junction crystalline silicon solar cell performance with silicon carbide (SiC) based front surface passivation. Int. J. Adv. Technol. Eng. Sci., 2: 626-630.
  11. Madan, J., R.S. Gupta and R. Chaujar, 2014. Influence of heterogeneous gate dielectric on hetero-dielectric-DMG-GAATFET for Improved tunneling current. Int. J. Adv. Technol. Eng. Sci., 2: 41-47.
  12. Kumar, A., N. Gupta and R. Chaujar, 2014. Investigation of frequency dependence on the noise response of a novel transparent gate recessed channel Mosfet. Int. J. Electr. Electron. Eng., 6: 7-13.
  13. Gupta, N., A. Kumar and R. Chaujar, 2014. Investigation of frequency dependent parameter of GEWE-SiNW Mosfet for microwave and RF applications. Int. J. Adv. Technol. Eng. Sci., 2: 35-40.
  14. Gupta, M. and R. Chaujar, 2013. Implementing true zero cycle branching in scalar and superscalar pipelined processors. ACEEE Int. J. Inf. Technol., 3: 50-55.
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  15. Agarwala, A. and R. Chaujar, 2013. Frequency dependence of noise performance metrices for gate electrode work function engineered recessed channel Mosfet. Int. J. Inf. Electron. Eng., 3: 432-435.
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  16. Agarwala, A. and R. Chaujar, 2012. Noise analysis of gate electrode work function engineered recessed channel (GEWE-RC) Mosfet. J. Phys. Conf. Ser., Vol. 367. 10.1088/1742-6596/367/1/012013.
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  17. Malik, P., R.S. Gupta, R. Chaujar and M. Gupta, 2011. Linearity-distortion analysis of GME-TRC Mosfet for high performance and wireless applications. J. Semicond. Technol. Sci., 11: 169-181.
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  18. Kumar, S.P., A. Agrawal, R. Chaujar, R.S. Gupta and M. Gupta, 2011. Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor. Microelectron. Reliab., 51: 587-596.
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  19. Malik, P., S.P. Kumar, R. Chaujar, M. Gupta and R.S. Gupta, 2010. Gate material engineered-trapizoidal recessed channel Mosfet for high-performance analog and RF applications. Microwave Opt. Technol. Lett., 52: 694-698.
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  20. Malik, P., R. Chaujar, M. Gupta and R.S. Gupta, 2010. Two-dimensional analytical drain current model for multilayered-gate material engineered trapezoidal recessed channel (MLGME-TRC) Mosfet: A novel design. World Acad. Sci. Eng. Technol. Int. J. Electr. Comput. Energetic Electron. Commun. Eng., 4: 733-737.
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  21. Malik, P., R. Chaujar, M. Gupta and R.S. Gupta, 2010. Physics based threshold voltage analysis of gate material engineered trapezoidal recessed channel (GME-TRC) nanoscale Mosfet and its multilayered gate architecture. Int. J. Microwave Opt. Technol., 5: 361-368.
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  22. Kaur, R., R. Chaujar, M. Saxena and R.S. Gupta, 2010. Hot-carrier reliability monitoring of DMG ISE SON Mosfet for improved analog performance. Microwave Opt. Technol. Lett., 52: 770-775.
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  23. Ghosh, P., R. Chaujar, S. Haldar, R.S. Gupta and M. Gupta, 2010. Analytical modeling of channel noise for gate material engineered surrounded/cylindrical gate (SGT/CGT) Mosfet. Int. J. Electr. Comput. Energetic Electron. Commun. Eng., 4: 751-754.
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  24. Chaujar, R., R. Kaur, M. Saxena, M. Gupta and R.S. Gupta, 2010. Design considerations and impact of technological parametric variations on RF/microwave performance of GEWE-RC Mosfet. Microwave Opt. Technol. Lett., 52: 652-657.
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  25. Kaur, R., R. Chaujar, M. Saxena and R.S. Gupta, 2009. Two dimensional simulation and analytical modeling of a novel ISE Mosfet with gate stack configuration. Microelectron. Eng., 86: 2005-2014.
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  26. Chaujar, R., R. Kaur, M. Saxena, M. Gupta and R.S. Gupta, 2009. Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale Mosfet: I. Semicond. Sci. Technol., Vol. 24. 10.1088/0268-1242/24/6/065005.
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  27. Chaujar, R., R. Kaur, M. Saxena, M. Gupta and R.S. Gupta, 2009. TCAD assessment of gate electrode workfunction engineered recessed channel (GEWE-RC) Mosfet and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation. Superlattices Microstruct., 46: 645-655.
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  28. Chaujar, R., R. Kaur, M. Saxena, M. Gupta and R.S. Gupta, 2009. Investigation of multi-layered-gate electrode workfunction engineered recessed channel (MLGEWE-RC) sub-50 nm Mosfet: A novel design. Int. J. Numer. Modell. Electron. Networks Devices Fields, 22: 259-278.
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  29. Kumar, S.P., A. Agrawal, R. Chaujar, M. Gupta and R.S. Gupta, 2008. Performance assessment and sub-threshold analysis of gate material engineered AlGaN/GaN Hemt for enhanced carrier transport efficiency. Microelectron. J., 39: 1416-1424.
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  30. Kumar, S.P., A. Agrawal, R. Chaujar, M. Gupta and R.S. Gupta, 2008. Analytical modeling and simulation of subthreshold behavior in nanoscale dual material gate AlGaN/GaN Hemt. Superlattices Microstruct., 44: 37-53.
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  31. Chaujar, R., R. Kaur, M. Saxena, M. Gupta and R.S. Gupta, 2008. Two-dimensional analytical sub-threshold model of multi-layered gate dielectric recessed channel (MLaG-RC) nanoscale Mosfet. Semicond. Sci. Technol., Vol. 23. 10.1088/0268-1242/23/4/045006.
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  32. Chaujar, R., R. Kaur, M. Saxena, M. Gupta and R.S. Gupta, 2008. TCAD assessment of gate electrode workfunction engineered recessed channel (GEWE-RC) Mosfet and its multilayered gate architecture-part I: hot-carrier-reliability evaluation. IEEE Trans. Electron Devices, 55: 2602-2613.
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  33. Chaujar, R., R. Kaur, M. Saxena, M. Gupta and R.S. Gupta, 2008. On-state and RF performance investigation of sub-50 nm L-DUMGAC MOSFET design for high-speed logic and switching applications. Semicond. Sci. Technol., Vol. 23. 10.1088/0268-1242/23/9/095009.
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  34. Chaujar, R., R. Kaur, M. Saxena, M. Gupta and R.S. Gupta, 2008. Laterally amalgamated DUal material GAte concave (L-DUMGAC) Mosfet for ULSI. Microelectron. Eng., 85: 566-576.
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  35. Chaujar, R., R. Kaur, M. Saxena, M. Gupta and R.S. Gupta, 2008. Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC Mosfet for RFIC design. Superlattices Microstruct., 44: 143-152.
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  36. Kumar, S.P., A. Agrawal, R. Chaujar, S. Kabra, M. Gupta and R.S. Gupta, 2007. Threshold voltage model for small geometry AlGaN/GaN HEMTs based on analytical solution of 3-D Poisson's equation. Microelectron. J., 38: 1013-1020.
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  37. Kaur, R., R. Chaujar, M. Saxena and R.S. Gupta, 2007. Unified subthreshold model for channel-engineered sub-100-nm advanced MOSFET structures. IEEE Trans. Electron Devices, 54: 2475-2486.
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  38. Kaur, R., R. Chaujar, M. Saxena and R.S. Gupta, 2007. Two-dimensional analytical model to characterize novel Mosfet architecture: Insulated shallow extension Mosfet. Semicond. Sci. Technol., 22: 952-962.
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  39. Kaur, R., R. Chaujar, M. Saxena and R.S. Gupta, 2007. Performance investigation of 50-nm insulated-shallow-extension gate-stack (ISEGaS) MOSFET for mixed mode applications. IEEE Trans. Electron Devices, 54: 365-368.
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  40. Kaur, R., R. Chaujar, M. Saxena and R.S. Gupta, 2007. Lateral channel engineered hetero material insulated shallow extension gate stack (HMISEGAS) Mosfet structure: High performance RF solution for MOS technology. Semicond. Sci. Technol., 22: 1097-1103.
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  41. Kaur, R., R. Chaujar, M. Saxena and R.S. Gupta, 2007. Hot-carrier reliability and analog performance investigation of DMG-USEGas Mosfet. IEEE Trans. Electron Devices, 54: 2556-2561.
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